1. Field of the Invention
The present invention relates to a semiconductor device having an internal voltage down-converting power supply, and more particularly, to a first stage input circuit (first stage input unit) of a DRAM (Dynamic Random Access Memory).
2. Description of the Background Art
A conventional semiconductor device which operates with a single external power supply is disclosed, for example, in Japanese Patent Laying-Open No. 5-189967. A semiconductor device shown herein by way of example is a DRAM.
FIG. 6 is a schematic block diagram partially showing a conventional DRAM. FIG. 6 also shows a power supply system of the DRAM.
Referring to FIG. 6, a portion of the conventional DRAM includes a voltage down-converting circuit (with small capacity) 2, a voltage down-converting circuit (with large capacity) 3, a last stage data output buffer circuit 4, an input buffer circuit 6, a peripheral circuit 8, and a memory cell array 7. Input buffer circuit 6 includes an input buffer circuit 5a provided in the first stage (hereinafter referred to as first stage input buffer circuit) and an input buffer circuit 5b provided in the subsequent stage (hereinafter referred to as subsequent stage input buffer circuit). Peripheral circuit 8 includes an internal control signal generating circuit 8a and a peripheral circuit (another peripheral circuit) 8b other than the internal control signal generating circuit.
An external power supply 1 supplies an external power supply potential (Vcc). Voltage down-converting circuit (with small capacity) 2 has relatively poor ability to supply current. Voltage down-converting circuit (with small capacity) 2 produce a down-converted potential from the external power supply potential Vcc, and supplies it as an internal power supply potential. Voltage down-converting circuit (with small capacity) 2 is steadily in an operative state.
Voltage down-converting circuit (with large capacity) 3 has relatively superior ability to supply current. Voltage down-converting circuit (with large capacity) 3 produces a down-converted potential from the external power supply potential Vcc and supplies it as an internal power supply potential, when the DRAM is in a selected state, that is, when an internal RAS (Row Address Strobe) signal is at an "L" level. Last stage data output buffer circuit 4 is a circuit provided in the last stage of a data output buffer circuit for externally outputting data.
First stage input buffer circuit 5a consists of a control signal input buffer, a data input signal input buffer, an X (row) address signal input buffer, and a Y (column) address signal input buffer. A control signal is an RAS signal, a CAS (Column Address Strobe) signal, a WE (Write Enable) signal, an OE (Output Enable) signal or the like.
The external power supply potential Vcc is supplied from external power supply 1 to first stage input buffer circuit 5a. An internal power supply potential is supplied from voltage down-converting circuit (with small capacity) 2 to subsequent stage input buffer circuit 5b during standby. An internal power supply potential is supplied from voltage down-converting circuit (with large capacity) 3 to subsequent input buffer circuit 5b during operation.
An internal power supply potential is supplied from voltage down-converting circuit (with small capacity) 2 to memory cell array 7 during standby. An internal power supply potential is supplied from voltage down-converting circuit (with large capacity) 3 to memory cell array 7 during operation.
Furthermore, an internal power supply potential is supplied from voltage down-converting circuit (with small capacity) 2 to peripheral circuit 8 during standby. An internal power supply potential is supplied from voltage down-converting circuit (with large capacity) 3 to peripheral circuit 8 during operation.
In the conventional DRAM (semiconductor device) described above, only the external power supply potential Vcc is supplied to first stage input buffer circuit 5a for receiving a control signal, a data input signal, an X address signal and a Y address signal (these signals are hereinafter collectively referred to as "an external signal" in some cases). As opposed to this, there is also a DRAM, as another example of the conventional DRAM, in which only an internal power supply potential is supplied to a first stage input buffer circuit (corresponding to first stage input buffer circuit 5a in FIG. 6).
As described above, only one of an internal power supply potential and an external power supply potential Vcc has been generally used as a potential supplied to first stage input buffer circuit 5a in the conventional semiconductor technique. In other words, a single power supply potential from a single power supply has been supplied to first stage input buffer circuit 5a.
In general, about 10% variation in the external power supply potential Vcc supplied from external power supply 1 with respect to a prescribed potential is tolerated according to the specifications. For example, in the case of a DRAM (semiconductor device) having an external power supply of a 5 V system, variation from 4.5 V to 5.5 V in an external power supply potential Vcc is permitted. Therefore, even if the external power supply potential Vcc is an unstable potential which varies in the range from 4.5 V to 5.5 V, first stage input buffer circuit 5a is ideally required to output completely the same potential information. Furthermore, in a logic circuit (for example, an inverter, an NOR gate, and an NAND gate), a threshold of an input signal for determining whether the input signal is at an "L" level or an "H" level is constant regardless of a value of the external power supply potential Vcc. For example, in the case of a general-purpose standard DRAM, a threshold for determining whether an "L" level or an "H" level is standardized so as to be in the range from 0.8 V to 2.4 V. It is noted that the logic circuit is generally used as first stage input buffer circuit 5a.
FIG. 7 is a schematic block diagram showing a conventional DRAM.
Referring to FIG. 7, the conventional DRAM includes a DQ pin 100, control signal pins 101, 102, 103 and 104, an address pin 105, a data input buffer circuit 16a, a data output buffer circuit 16b, an RAS buffer circuit 15a, a CAS buffer circuit 15b, a WE buffer circuit 15c, an OE buffer circuit 15d, a Y address buffer circuit 19, an X address buffer circuit 20, a voltage down-converting circuit (with small capacity) 2, a voltage down-converting circuit (with large capacity) 3, another peripheral circuit 8b, an internal control signal generating circuit 18, a Y address decoder 21, a sense amplifier 23, an X address decoder 22, and a memory cell array 17. It is noted that a portion similar to that in FIG. 6 is denoted by the same reference and description thereof will not be repeated.
Data input buffer circuit 16a, RAS buffer circuit 15a, CAS buffer circuit 15b, WE buffer circuit 15c, OE buffer circuit 15d, Y address buffer circuit 19 and X address buffer circuit 20 correspond to input buffer circuit 6 shown in FIG. 6. Internal control signal generating circuit 18 is a part of internal control signal generating circuit 8a shown in FIG. 6.
A data input/output (I/O) signal 9 is a signal including data to be input externally or data to be output externally. A signal to be input externally included in data I/O signal 9 is called a data input signal. A signal to be output externally included in data I/O signal 9 is called a data output signal. Data input buffer circuit 16a receives data input signal 9 and inputs data to memory cell array 17. Data output buffer 16b receives data from memory cell array 17 and outputs data output signal 9.
RAS buffer circuit 15a is an input buffer circuit to which an RAS signal 10 for controlling introduction of a row (X) address is input. RAS buffer circuit 15a outputs an internal RAS signal to internal control signal generating circuit 18, based on the RAS signal 10.
CAS buffer circuit 15b is an input buffer circuit to which a CAS signal 11 for controlling introduction of a column (Y) address is input. CAS buffer circuit 15b outputs an internal CAS signal to internal control signal generating circuit 18, based on the CAS signal 11.
WE buffer circuit 15c is an input buffer circuit to which a WE signal 12 for controlling read/write operation is input. WE buffer circuit 15c outputs an internal WE signal to internal control signal generating circuit 18, based on the WE signal 12.
OE buffer circuit 15d is an input buffer circuit to which an OE signal 13 for controlling output of data is input. OE buffer circuit 15d outputs an internal OE signal to internal control signal generating circuit 18, based on the OE signal 13. It is noted that RAS signal 10, CAS signal 11, WE signal 12 and OE signal 13 are hereinafter collectively referred to as a control signal in some cases.
Internal control signal generating circuit 18 outputs an internal control signal 4, based on the internal RAS signal, the internal CAS signal, the internal WE signal or the internal OE signal.
Address pin 105 receives an address signal 14 including an X (row) address signal and a Y (column) address signal for designating an address. Y address buffer circuit 19 receives as an input a Y address signal YL of address signal 14 and outputs a signal based on the Y address signal YL to Y address decoder 21. X address buffer 20 receives as an input an X address signal XL of address signal 14 and outputs a signal based on the X address signal XL to X address decoder 22.
Sense amplifier 23 senses information held in a memory cell located at designated coordinates. The information read by sense amplifier 23 is output through data output buffer circuit 16b to DQ pin 100 for inputting/outputting data.
Memory cell array 17 includes a plurality of memory cells for storing information. Memory cell array 17 is similar to memory cell array 7 shown in FIG. 6. RAS signal 10, CAS signal 11, WE signal 12 and OE signal 13 are control signals in a sense that they control internal operation of the DRAM. Furthermore, data input signal 9, control signals 10-13 and address signal 14 are external signals in a sense that they are input externally.
In this DRAM, all the control signals (RAS signal 10, CAS signal 11, WE signal 12 and OE signal 13) out of the above described external signals (address signal 14 for controlling designation of coordinates in memory cell array 17, data input signal 9, RAS signal 10, CAS signal 11, WE signal 12 and OE signal 13) activate chip operation according to each control signal by transition from an "H" level to an "L" level.
Address signal 14 and data input signal 9 activate subsequent stage input buffer circuit 5b (FIG. 6) by any one of transitions from an "H" level to an "L" level and from an "L" level to an "H" level. In addition, first stage input buffer circuit 5a (FIG. 6) must receive a signal during operation of subsequent stage input buffer circuit 5b, peripheral circuit 8 (FIG. 6) and the like within the DRAM.
Thus, first stage input buffer circuit 5a will be subject to variation in a power supply potential which is caused by such internal operation. Accordingly, first stage input buffer circuit 5a which is required to receive a signal during internal operation need operate more stably in a wider range of variation in a power supply potential than the range of variation in an external power supply potential according to the specifications, compared to subsequent stage input buffer circuit 5a which is not required to receive a signal during internal operation.
As described above, only external power supply 1 or only an internal power supply is used as a power supply of first stage input buffer circuit 5a. Problems caused in the case where a potential is supplied only from external power supply 1 as a power supply potential of first stage input buffer circuit 5a as shown in FIG. 6 will now be described.
First stage input buffer circuit 5a to which address signal 14 and data input signal 9 are input is subject to the specification-tolerated range of variation in the external power supply potential Vcc supplied from external power supply 1. Furthermore, first stage input buffer circuit 5a for receiving address signal 14 and data input signal 9 must receive a signal (address signal 14 and data input signal 9) during operation of subsequent stage input buffer circuit 5b in input buffer circuit 6, peripheral circuit 8 and the like.
As can be seen from the above description, first stage input buffer circuit 5a for receiving address signal 14 and data input signal 9 has many factors causing circuit operation and output information thereof to be unstable. Accordingly, it has been difficult to achieve stable operation of first stage input buffer circuit 5a which is required to receive a signal (address signal 14 and data input signal 9) during internal operation.
Problems caused in the case where a potential is supplied only from an internal power supply as a power supply potential of first stage input buffer circuit 5a will now be described. As to the voltage down-converting circuits for generating an internal power supply potential, only a voltage down-converting circuit with relatively small capacity is generally caused to operate during standby period when the ability to supply a power supply potential may be poor as shown in FIG. 6, so that current consumption is suppressed by this voltage down-converting circuit.
In a first stage input buffer circuit (corresponding to first stage input buffer circuit 5a of FIG. 6), however, an input signal is permitted to be at an intermediate level such as 2.4 V and 0.8 V. Therefore, through current flows in the first stage input buffer circuit due to the input signal at an intermediate level such as 2.4 V and 0.8 V. In other words, through current is permitted to flow in the first stage input buffer circuit to some degree.
Accordingly, leak current due to this through current must be supplemented, and ability to supply a power supply potential, which is superior to ability to supply a power supply potential which is required to maintain supply of an internal power supply potential necessary for the first stage input buffer circuit in the absence of leak current, must be provided in a voltage down-converting circuit with small capacity. Therefore, sufficient reduction in power consumption of a voltage down-converting circuit with small capacity has not been achieved, resulting in increase in current consumption during standby.
In view of the above description, in the conventional semiconductor device (DRAM), that is, in the case where a power supply potential is supplied directly from external power supply 1 to first stage input buffer circuit 5a for receiving address signal 14, data input signal 9 and control signals 10-13, influence of variation in the external power supply potential Vcc supplied from external power supply 1 on subsequent stage input buffer circuit 5b has been required to be suppressed.
In addition, in the conventional semiconductor device (DRAM), that is, in the case where only an internal power supply potential produced from the external power supply potential Vcc is supplied as a power supply potential to first stage input buffer circuit Sa for receiving address signal 14, data input signal 9 and control signals 10-13, suppression of power consumption for causing an internal down-converted potential generating circuit (voltage down-converting circuit) for producing an internal power supply potential to operate has not been achieved during standby.